1. Field of the Invention
The present invention relates to rise and fall times in integrated circuits, and more particularly, to a system for generating an ideal rise and fall time that is independent of temperature and voltage, and a corresponding method.
2. Description of the Prior Art
In an Integrated Circuit (IC), rise and fall times are an indication of how fast the IC can switch between different logic states. ICs, however, are affected by changes in temperate, voltage etc., which also leads to some variation in rise and fall times. In order to avoid this problem, it is necessary to create rise and fall times that are not affected by variations in temperature and voltage. By creating the ideal rise and fall times on-chip, and then using the rise and fall times to calibrate, problems of noise can be avoided.
Please refer to FIG. 1. FIG. 1 is a diagram of a prior art solution for the problem of noise. FIG. 1 shows a system 100 comprising a first P transistor P1 and a second P transistor P2 both coupled to a voltage supply Vcc. The system 100 also shows a first N transistor N1 coupled to P1 and a second N transistor coupled to the voltage supply Vcc. An input drives P2 and N2, and the gates of P1 and N1 are coupled to P2 and N2 respectively. In typical CMOS devices, as temperature rises the rise and fall times will slow down. As the devices P1 and N1 are an inversion stage driven by CMOS logic, and the current is proportional to temperature, the increasing current will also increase the rise and fall times by the same amount the increase in temperature causes them to slow down. Therefore, the rise and fall times remain constant.
This system, however, only compensates for a change in temperature. If the voltage supply were to change, there would be a corresponding shift in the rise and fall times. It is therefore necessary to design a circuit for creating rise and fall times that are independent of both temperature and voltage variation.